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INTEGRATED CIRCUITS
DATA SHEET
SAA7212 Integrated MPEG AVG decoder
Preliminary specification Supersedes data of 1998 Feb 18 File under Integrated Circuits, IC02 1998 Sep 07
Philips Semiconductors
Preliminary specification
Integrated MPEG AVG decoder
FEATURES General features * Single external Synchronous DRAM organized as 1 M x 16 interfacing at 81 MHz. Due to efficient memory use in MPEG decoding, more than 1 Mbit available for graphics * Fast 16-bit data + 8-bit address interface with external controller on 27 MHz. Sustained data rate to external SDRAM 9 Mbytes/s in bursts of 128 bytes * Dedicated input for audio and video in PES or ES in byte wide. Data input rate: 9 Mbytes/s in byte mode. Accompanying strobe signals distinguish between audio and video data * Dedicated compressed data input compatible with the VLSI VES2020/2030 demultiplexers; video is received in byte format and audio serially * Audio and/or video can also be input via the CPU interface in PES/ES in 8 or 16-bit parallel format up to a peak data rate of 9 Mbytes/s * Single 27 MHz external clock for time base reference and internal processing. Internal system time base at 90 kHz can be synchronized via CPU port. All required decoding and presentation clocks are generated internally * Flexible memory allocation under control of the external CPU enables optimized partitioning of memory for different tasks * Boundary scan testing implemented * External SDRAM self test * Supply voltage 3.3 V * Package QFP160. CPU related features * 16 bits data, 8 bits address, or 16 bits multiplexed bus. Motorola 68xxx and Intel x 86 compatible. * Support fast DMA transfer * Flexible bidirectional interface to external SDRAM. Minimum sustained rate is 9 Mbytes/s * Enhanced block mover allows 3 D data move in the external SDRAM. Picture move/Graphic bit maps construction can be done with minimum CPU support. MPEG2 system features
SAA7212
* Parsing of MPEG2 PES and MPEG1 packet streams * Double system time clock counters * Stand-alone or supervised audio/video synchronization * Processing of errors flagged by channel decoding section * Support for retrieval of PES header. MPEG2 video features * Decoding of MPEG2 video up to main level, main profile * Output picture format: CCIR-601 4 : 2 : 2 interlaced pictures. Picture format 720 x 576 at 50 Hz or 720 x 480 at 60 Hz * Support of constant and variable bit rates up to 15 Mbits/s * Stand-alone or CPU controlled mode for decoding/display processes * Stand-alone mode can be used by applications requiring still pictures manipulations * Output interface at 8-bit wide, 27 MHz UYVY multiplexed bus * Horizontal and vertical pan and scan allows the extraction of a window from the coded picture * Flexible horizontal scaling from 0.5 up to 4 allows easy aspect ratio conversion including support for 2.21 : 1 aspect ratio movies. In case of shrinking an anti-aliasing pre-filter is applied * Vertical scaling with fixed factors 0.5, 1 or 2. Factor 0.5, realizing picture shrink. Factor 2 can be used for up-conversion of pictures with 288 (240) lines or less. * Vertical down-scaling with 0.75 factor, realizing letter box conversion * Horizontal and vertical scaling can be combined to scale pictures to 14 their original size, thus freeing up screen space for graphic applications like electronic program guides * Non full screen MPEG pictures will be displayed in a box of which position and background colour are adjustable by the external microcontroller * Nominal video input buffer size for ml@mp 2.7 Mbit * Video output may be slaved to internally (master) generated or externally (slave) supplied HV synchronization signals. The position of active video is programmable. Display phase is not affected by MPEG timebase changes.
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Preliminary specification
Integrated MPEG AVG decoder
* Video output direct connectable to SAA718x encoder family * Various trick modes under control of external microcontroller in stand-alone mode: - Freeze field/frame on I or P pictures; restart on I picture - Freeze field on B pictures; restart on the next I or P picture. - Scanning and decoding of I or I + P pictures in a IBP sequence - Single step mode - Repeat/skip field for time base correction. MPEG2 audio features * Decoding of 2 channels, layer I and II MPEG audio. Support for mono, stereo, intensity stereo and dual channel mode. * Constant and variable bit rates up to 448 kbit/s * Supported audio sampling frequencies: 48, 44.1, 32, 24, 22.05 and 16 kHz * CRC error detection * 3 decoding modes for dual channel streams: decoding of CH1 only, decoding of CH2 only and decoding of both CH1 and CH2 * Storage of last 54 bytes in ancillary data field * Dynamic Range Control (DRC) at output * Independent channel volume control and programmable inter channel crosstalk through a baseband audio processing unit * Muting possibility via external controller. Automatic muting in case of errors or data lack. * Generation of `beeps' with programmable tone height, duration and amplitude * Serial two channel digital audio output with 16, 18, 20 or 22 bits per sample, compatible either to I2S or Japanese formats. Output can be set to high-impedance mode via the external controller. * Serial SPDIF audio output. Output can be set to high-impedance mode. * Clock output 256 or 384 x fs for external DA converter. Output can be set to high-impedance mode. * Audio FIFO in external SDRAM. Programmable buffer size, at least 64 kbit is available. * Synchronization modes: PTS controlled, PTS free running, software controlled, buffer controlled * PTS register can be set via external controller 1998 Sep 07 3
SAA7212
* Programmable processing delay compensation * Software controlled stop and restart functions. Graphics features * Graphics are presented in boxes independent of video format * Screen arrangement of boxes is determined by display list mechanism which allows for multiple boxes, background loading, fast switching, scrolling and fading of regions * Support of 2, 4, 8-bit/pixel in fixed bit maps format or coded in accordance to the DVB variable/run length standard for region based graphics * Display colours are obtained via colour look up tables. CLUT output is YUVT at 8-bit for each signal component thus enabling 16 M different colours and 6-bit for T which gives 64 mixing levels with video, (T = transparency). * Bit-map table mechanism to specify a sub set of entries if the CLUT is larger than required by the coded bit pattern. Supported bit-map tables are 16 to 256, 4 to 256 and 4 to 16. * Graphics boxes may not overlap vertically. If 256 entry CLUT has to be down loaded, a vertical separation of 1 line is mandatory. * Optimized memory utilization in MPEG video decoding allows for a storage capacity of 1.2 Mbit for graphics bit maps. Flexibility in memory control enables larger capacity in a lot of applications. Moreover variable length/run length encoding makes better use of available memory capacity for graphics bit maps thus making full screen graphics at 8-bit/pixel feasible. * Fast CPU access (9 Mbytes/s) enables full 1.2 Mbit bit map update within 20 ms * Internal support for fast block moves in external SDRAM * Graphics mechanism can be used for signal generation in the vertical blanking interval. Useful for teletext, wide screen signalling, closed caption, etc. * Support for a single down loadable cursor of 1k pixel with programmable shape. Supported shapes are 8 x 128 pixels, 16 x 64 pixels, 32 x 32 pixels, 64 x 16 pixels and 128 x 8 pixels. * Cursor colours obtained via 4 entry CLUT with YUVT at 6,4,4 respectively 2 bits. Mixing of cursor with video + graphics in 4 levels. * Cursor can be moved freely across the screen without overlapping restrictions.
Philips Semiconductors
Preliminary specification
Integrated MPEG AVG decoder
APPLICATIONS * Tbf. GENERAL DESCRIPTION
SAA7212
The SAA7212 is an MPEG2 source decoder which combines audio decoding and video decoding. Additionally to these basic MPEG functions it also provides means for enhanced graphics and/or on-screen display (OSD). Due to an optimized architecture for audio and video decoding, maximum capacity in external memory and processing power from the external CPU is available for graphics support. QUICK REFERENCE DATA SYMBOL VDD IDD(tot) fclk PARAMETER functional supply voltage total supply current; VDD = 3.3 V device clock frequency - MIN. 3.0 TYP. 3.3 tbf - MAX. 3.6 V mA UNIT
-30 ppm 27.0
+30 ppm MHz
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA7212H QFP160 DESCRIPTION plastic quad flat package; 160 leads (lead length 1.95 mm); body 28 x 28 x 3.4 mm; high stand-off height VERSION SOT322-1
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Philips Semiconductors
Preliminary specification
Integrated MPEG AVG decoder
BLOCK DIAGRAM
SAA7212
SDRAM
Memory interface Video input buffer and sync from Demux Audio/video interface Video Decoder System time base unit
Display unit
to/from external CPU
Host interface SDRAM access unit Clock generation Graphics unit to digital encoder to audio DAC
Audio Decoder
JTAG
Audio input buffer and sync
Fig.1 Block diagram.
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Preliminary specification
Integrated MPEG AVG decoder
PINNING SYMBOL MUX CPU_TYPE DMA_ACK DMA_REQ DMA_DONE DMA_RDY VSS CS DS AS RWN DTACK VDD IRQ 0 IRQ 1 V_REQ A_REQ VSS VSSCO VDDCO DATA 0 DATA 1 DATA 2 DATA 3 VDD DATA 4 DATA 5 DATA 6 DATA 7 VSS DATA 8 DATA 9 DATA 10 DATA 11 VDD DATA 12 DATA 13 DATA 14 DATA 15 VSS 1998 Sep 07 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 multiplexed/non multiplexed bus Intel/Motorola selection DMA acknowledge DMA request DMA end DMA ready ground for pad ring chip select. data strobe address strobe read/write data acknowledge 3.3 V supply for pad ring individually maskable interrupts individually maskable interrupts compressed video data request compressed audio data request ground for pad ring ground for core logic 3.3 V supply for core logic CPU data interface CPU data interface CPU data interface CPU data interface 3.3 V supply for pad ring CPU data interface CPU data interface CPU data interface CPU data interface ground for pad ring CPU data interface CPU data interface CPU data interface CPU data interface 3.3 V supply for pad ring CPU data interface CPU data interface CPU data interface CPU data interface ground for pad ring 6 DESCRIPTION
SAA7212
Philips Semiconductors
Preliminary specification
Integrated MPEG AVG decoder
SAA7212
SYMBOL ADDRESS 1 ADDRESS 2 ADDRESS 3 ADDRESS 4 VDD ADDRESS 5 ADDRESS 6 ADDRESS 7 ADDRESS 8 VSS VSSCO VDDCO SDRAM_DATA 0 SDRAM_DATA 15 SDRAM_DATA 1 VDD SDRAM_DATA 14 SDRAM_DATA 2 SDRAM_DATA 13 VSS SDRAM_DATA 3 SDRAM_DATA 12 SDRAM_DATA 4 VDD SDRAM_DATA 11 SDRAM_DATA 5 SDRAM_DATA 10 VSS SDRAM_DATA 6 SDRAM_DATA 9 SDRAM_DATA 7 VDD SDRAM_DATA 8 SDRAM_WE SDRAM_CAS VSS SDRAM_RAS SDRAM_UDQ VDD READ_IN READ_OUT 1998 Sep 07
PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 CPU address interface CPU address interface CPU address interface CPU address interface 3.3 V supply for pad ring CPU address interface CPU address interface CPU address interface CPU address interface ground for pad ring ground for core logic 3.3 V supply for core logic SDRAM data SDRAM data SDRAM data 3.3 V supply for pad ring SDRAM data SDRAM data SDRAM data ground for pad ring SDRAM data SDRAM data SDRAM data 3.3 V supply for pad ring SDRAM data SDRAM data SDRAM data ground for pad ring SDRAM data SDRAM data SDRAM data 3.3 V supply for pad ring SDRAM data SDRAM write enable SDRAM column address strobe ground for pad ring SDRAM row address strobe SDRAM write mask 3.3 V supply for pad ring read command in read command out 7
DESCRIPTION
Philips Semiconductors
Preliminary specification
Integrated MPEG AVG decoder
SAA7212
SYMBOL VSS CP81MEXT CP81M VDD SDRAM_ADDR 8 SDRAM_ADDR 9 SDRAM_ADDR 11 VSS SDRAM_ADDR 7 SDRAM_ADDR 10 SDRAM_ADDR 6 VDD SDRAM_ADDR 0 SDRAM_ADDR 5 SDRAM_ADDR 1 VSS SDRAM_ADDR 4 SDRAM_ADDR 2 SDRAM_ADDR 3 VSSCO VDDCO VDD Test 5 Test 6 HS VS VSS YUV 0 YUV 1 YUV 2 YUV 3 VDD YUV 4 YUV 5 YUV 6 YUV 7 Test 4 GRPH Test 3 VDDAN VSSAN 1998 Sep 07
PIN 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 ground for pad ring
DESCRIPTION 81 MHz SDRAM clock return path 81 MHz SDRAM memory clock 3.3 V supply for pad ring SDRAM address SDRAM address SDRAM address ground for pad ring SDRAM address SDRAM address SDRAM address 3.3 V supply for pad ring SDRAM address SDRAM address SDRAM address ground for pad ring SDRAM address SDRAM address SDRAM address ground for core logic 3.3 V supply for core logic 3.3 V supply for pad ring IC test interface (see note 2) IC test interface (see note 2) horizontal synchronization vertical synchronization ground for pad ring YUV video output at 27 MHz YUV video output at 27 MHz YUV video output at 27 MHz YUV video output at 27 MHz 3.3 V supply for pad ring YUV video output at 27 MHz YUV video output at 27 MHz YUV video output at 27 MHz YUV video output at 27 MHz IC test interface (see note 3) indicator for graphics information IC test interface (see note 4) 3.3 V supply for analog blocks ground for analog blocks 8
Philips Semiconductors
Preliminary specification
Integrated MPEG AVG decoder
SAA7212
SYMBOL VSS CLK VSS TCK TRST TMS TDO TDI VDD Test 0 Test 1 Test 2 AUDDEN A_DATA VDD RESET FSCLK VDDCO VSSCO SCK SD VSS WS SPDIF ERROR V_STROBE VDD AV_DATA 0 AV_DATA 1 AV_DATA 2 AV_DATA 3 VSS AV_DATA 4 AV_DATA 5 AV_DATA 6 AV_DATA 7 A_STROBE VDD
PIN 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 ground for pad ring 27 MHz Clock input ground for pad ring boundary scan test clock boundary scan test reset boundary scan test mode select boundary scan test data output boundary scan test data input 3.3 V supply for pad ring IC test interface (see note 4) IC test interface (see note 4) IC test interface (see note 4)
DESCRIPTION
synchronization of the serial audio input (A_DATA) serial audio input 3.3 V supply for pad ring hard reset input, active LOW 256 or 384fs (audio sampling) 3.3 V supply for core logic ground for core logic serial audio clock serial audio data output ground for pad ring word select digital audio output flag for bitstream error. video strobe 3.3 V supply for pad ring MPEG stream input port MPEG stream input port MPEG stream input port MPEG stream input port ground for pad ring MPEG stream input port MPEG stream input port MPEG stream input port MPEG stream input port audio strobe 3.3 V supply for pad ring
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Philips Semiconductors
Preliminary specification
Integrated MPEG AVG decoder
Notes
SAA7212
1. 5 V tolerant outputs swing between VSS and VDD but 5 V tolerant input can receive signal swinging between VSS and 3.3 V or VSS and 5 V. 2. Should be left open in normal mode. 3. Should be tied up to VDD in normal mode. 4. Should be tied down to ground in normal mode.
160
handbook, halfpage
121
1
120
SAA7212H
40
81
MGL400
41
Fig.2 Pin configuration.
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Preliminary specification
Integrated MPEG AVG decoder
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD Vn(max) Ptot Tstg Tamb supply voltage voltage on all pins total power dissipation IC storage temperature operating ambient temperature Tamb = 25 C PARAMETER CONDITIONS 0 - -55 0 MIN. -0.5 5 1 150 70 TYP. +5
SAA7212
MAX. tbf tbf tbf tbf tbf
UNIT V V W C C
THERMAL CHARACTERISTICS SYMBOL Rth(j-a) HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. CHARACTERISTICS SYMBOL Supply VDD IDD(tot) Inputs VIH(5V tolerant) VIH VIL(5V tolerant) VIL IL Ci Outputs VOH(5V tolerant) VOH VOL(5V tolerant) VOL DC timing Tcy cycle time duty factor - 40 37.037 - - 60 ns % output voltage HIGH output voltage HIGH output voltage LOW output voltage LOW 2.4 VDD - 0.4 - - - - - - - - 0.4 0.4 V V V V input voltage HIGH input voltage HIGH input voltage LOW input voltage LOW leakage current input capacitance 2.0 0.7VDD -0.5 -0.5 - 0 - - - - - - 6.5 VDD+2.0 0.8 0.3VDD 20 10 V V V V A pF functional supply voltage total supply current; VDD = 3.3 V 3.0 - 3.3 tbf 3.6 - V mA PARAMETER MIN. TYP. MAX. UNIT PARAMETER thermal resistance from junction to ambient in free air VALUE 30 UNIT K/W
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Preliminary specification
Integrated MPEG AVG decoder
APPLICATION INFORMATION
SAA7212
4-Mbit EPROM
4-Mbit DRAM
16-Mbit SDRAM
16 8+3 Irq 4
addr 12
data ctrl 16
CPU + DEMUX
8 Strobe 2
SAA7212
valid YUV H,V
I2S
AUDIO D/A
L R
27.0 MHz
high speed data
27 MHz H,V,FP TTX/TTXRQ
SAA7183
(euro-denc)
CVBS Y/C RGB
I2C-bus
Fig.3 Application diagram
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Preliminary specification
Integrated MPEG AVG decoder
SAA7212
CP81MEXT CP81M READ_OUT READ_IN SDRAM_UDQ SDRAM_CAS SDRAM_RAS SDRAM_CS SDRAM_WE SDRAM_DATA0 ....... SDRAM_DATA15 SDRAM_ADDR11 SDRAM_ADDR10 SDRAM_ADDR9 SDRAM_ADDRA8 SDRAM_ADDR7 .... SDRAM_ADDR0 CLK CKE LDQM UDQM CAS RAS CS
SDRAM 16-Mbit TSSOP II 50 pins DQ0 400 mil ....
WE DQ15 A11 A10 A9 A8 A7 .... A0
The board should be designed to insure a similar load on the CP81M and READ_OUT pins as well as a similar fly time between the CP81M and CP81MEXT pins on one side and the READ_OUT and READ_IN pins on the other side.
Fig.4 Connection SAA7212 SDRAM.
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Preliminary specification
Integrated MPEG AVG decoder
PACKAGE OUTLINE QFP160: plastic quad flat package; 160 leads (lead length 1.95 mm); body 28 x 28 x 3.4 mm; high stand-off height
SAA7212
SOT322-1
c
y
X
A 120 121 81 80 ZE
e E HE A A2 A1 (A 3) Lp L detail X 41 1 bp D HD wM ZD B vM B 40 vM A
wM bp pin 1 index 160
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT322-1 REFERENCES IEC JEDEC MO112DD1 EIAJ EUROPEAN PROJECTION A max. 3.95 A1 0.40 0.25 A2 3.70 3.15 A3 0.25 bp 0.40 0.25 c 0.23 0.13 D (1) 28.1 27.9 E (1) 28.1 27.9 e 0.65 HD 32.2 31.6 HE 32.2 31.6 L 1.95 Lp 1.1 0.7 v 0.3 w 0.15 y 0.1 Z D(1) Z E (1) 1.5 1.1 1.5 1.1 8 0o
o
ISSUE DATE 95-02-04 97-08-04
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Preliminary specification
Integrated MPEG AVG decoder
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. Wave soldering
SAA7212
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm. If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
Integrated MPEG AVG decoder
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7212
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
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Philips Semiconductors
Preliminary specification
Integrated MPEG AVG decoder
NOTES
SAA7212
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Philips Semiconductors
Preliminary specification
Integrated MPEG AVG decoder
NOTES
SAA7212
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Preliminary specification
Integrated MPEG AVG decoder
NOTES
SAA7212
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Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545104/750/02/pp20
Date of release: 1998 Sep 07
Document order number:
9397 750 04068

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